AMD K5 Instrukcja Użytkownika Pobierz pdf (Strona 43)

18522F/0—Jan1997 AMD-K5 Processor Data Sheet

PRELIMINARY INFORMATION

The INVD instruction invalidates the entire cache and gener-

ates a Flush special cycle to instruct the L2 cache to invalidate

all lines.

The WBINVD instruction writes back and invalidates all cache

lines, generates a Write Back special cycle to instruct the L2

cache to write back all lines, and then generates a Flush spe-

cial cycle to instruct the L2 cache to invalidate all lines.

Read Cycles The cache response to processor-generated reads is described

in Table 8. Processor reads that hit in the data cache require

no external data cycle. The data is provided by the cache. Pro-

cessor reads that miss in the data cache generate a read-allo-

cate operation, including an external bus cycle. The action of

the cache is dependent on the system response to that cycle.

The cache state transition for read cycles is also described in

Table 8.

A read allocate begins by selecting the way in the cache to be

replaced at random.

If the selected line is not modified, the data is discarded and

the read of the new line is begun. When the first quad word of

Table 8. Processor Reads to Data Cache

State CACHE KEN WB/WT PWT Next State Note

Mx x x x M 1

Ex x x x E 1

Sx x x x S 1

I00 1 0 E 2

I00 0 x S 3

I1x x x I 4

Ix1 x x I4, 5

Notes:

1. A read cycle hit: Data is provided directly from the cache.

2. A read cycle miss: Selects the line for replacement; writes back the replaced line if it is modified

(otherwise, discards the line). The line is cached as writeback.

3. A read cycle miss: Selects the line for replacement; writes back the replaced line if it is modified

(otherwise discards the line). The line is cached as writethrough.

4. A read cycle miss: The line is not cacheable.

5. Within the cache directory, the Invalid state indicates that the cache entry contains no valid

data. For purposes of hit/miss determination, the Invalid state indicates that the referenced

cache line is not present in the cache. When a line is selected for replacement, all invalid ways

are selected before any valid data is displaced from the cache.

1 2 ... 38 39 40 41 42 43 44 45 46 47 48 ... 99 100

Brak uwag

AMD K5 Instrukcja Użytkownika Strona 43