AMD K5 Instrukcja Użytkownika Pobierz pdf (Strona 53)

18522F/0—Jan1997 AMD-K5 Processor Data Sheet

PRELIMINARY INFORMATION

The LOCK pin is asserted for the duration of locked accesses.

Note also that at least one dead cycle will always be present

between consecutive locked atomic read-modify-write opera-

tions. This will be noted by the negating of the LOCK pin for at

least one clock period between consecutive locked accesses.

Locked Operation to

Cached Lines

When a locked operation to a cached line occurs, the processor

invalidates the line and determines whether the line is modi-

fied. If the line is modified, it is written back to memory. LOCK

is not asserted during the writeback operation. LOCK is then

asserted and the locked read-modify-write operations are per-

formed. The line is not cached during these operations. SCYC

is asserted for misaligned locked transfers.

Bus Hold HOLD, illustrated in Figure 9 on page 44, is used to inform the

processor that another bus device desires to be bus master. If

HOLD is asserted, the processor completes all pending bus

cycles and acknowledges release of the bus by asserting

HLDA. When the bus is released, the processor floats the fol-

lowing outputs:

These are the same outputs that are floated when BOFF is

asserted. These outputs provide status information, but do not

participate in the external memory system access.

■ A31–A3

■ ADS

■ AP

■ BE7–BE3

■ CACHE

■ D/C

■ D63–D0

■ DP7–DP0

■ LOCK

■ M/IO

■ PCD

■ PWT

■ SCYC

■ W/R

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AMD K5 Instrukcja Użytkownika Strona 53