AMD K5 Instrukcja Użytkownika Strona 78
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- Data Sheet 1
- Trademarks: 2
- Contents 3
- 10.4 RESET, TCK, TRST 6
- List of Figures 7
- List of Tables 9
- 18522F/0—Jan1997 10
- PRELIMINARY INFORMATION 10
- 1 AMD-K5™ Processor Features 11
- 1.2 High-Performance Design 12
- 1.3 Compatibility 12
- Revision History 13
- 2 Block Diagram 14
- 3 Ordering Information 15
- 4 Architectural Introduction 16
- 4.3 Register Renaming 17
- 4.6 Cache Architecture 18
- 4.7 Branch Prediction 19
- 4.9 Reorder Buffer 20
- 4.10 Register File 21
- 5 CPU Identification 22
- 6 Logic Symbol Diagram 23
- 7 Signal Descriptions 24
- AMD-K5 Processor Data Sheet 35
- Table 2. Output Pins 35
- Table 3. Input/Output Pins 36
- Table 4. Test Pins 36
- Table 5. Bus Cycle Definition 36
- Table 6. Special Cycles 37
- 8 Processor Operation 38
- 8.3 Cache Protocol 41
- 8.4 Data Cache Coherency 42
- 8.5 External Bus Description 46
- 8.6 Bus Cycles 48
- 8.7 System Management Mode 61
- Table 12. SMM Save Area Map 62
- 8.8 Am486 64
- 9 Electrical Data 66
- 9.2 Absolute Maximum Ratings 67
- 9.3 Operating Ranges 67
- 10 Switching Characteristics 69
- 10.2 60-MHz Bus Operation 72
- 10.3 50-MHz Bus Operation 74
- Figure 15. Diagrams Key 78
- Figure 16. CLK Waveform 78
- Figure 21. TCK Waveform 81
- Figure 22. TRST Timing 81
- 11 Timing Diagrams 82
- Figure 39. Special Cycle 89
- Start blank 90
- 13 Physical Dimensions 94
- 15 Pin Designations (Model 0) 96
- Functional Grouping 98
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