AMD Duron Instrukcja Użytkownika Pobierz pdf (Strona 17)

Chapter 2 Interface Signals 5

23802E—September 2000 AMD Duron™ Processor Data Sheet

Preliminary Information

2 Interface Signals

2.1 Overview

The AMD system bus architecture is designed to deliver

superior data movement bandwidth for value x86 platforms.

The system bus architecture consists of three high-speed

channels (a unidirectional processor request channel, a

unidirectional probe channel, and a 72-bit bidirectional data

channel, including 8-bit error code correction [ECC]

protection), source-synchronous clocking, and a packet-based

protocol. In addition, the system bus supports several control,

clock, and legacy signals. The interface signals use an

impedance controlled push-pull low-voltage swing signaling

technology contained within the Socket A mechanical

connector, which is mechanically compatible with the

industry-standard SC242 connector. For more information, see

“AMD System Bus Signals” on page 6, Chapter 9, “Pin

Descriptions” on page 41, and the AMD System Bus

Specification, order# 21902.

2.2 Signaling Technology

The AMD system bus uses a low-voltage, swing signaling

technology, which has been enhanced to provide larger noise

margins, reduced ringing, and variable voltage levels. The

signals are push-pull and impedance compensated. The signal

inputs use differential receivers, which require a reference

voltage (V

REF

). The reference signal is used by the receivers to

determine if a signal is asserted or deasserted by the source.

Termination resistors are not needed because the driver is

impedance matched to the motherboard and a high impedance

reflection is used at the receiver to bring the signal past the

input threshold.

For more information about pins and signals, see Chapter 9,

“Pin Descriptions” on page 41.

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