AMD Duron Instrukcja Użytkownika Pobierz pdf (Strona 26)

14 Power Management Chapter 4

AMD Duron™ Processor Data Sheet 23802E—September 2000

Preliminary Information

3. When the special cycle is received by the system controller,

the system controller deasserts CONNECT, initiating a bus

disconnect to the processor.

4. The processor replies to the system controller by

deasserting PROCRDY, approving the bus disconnect

request.

5. The system controller asserts CLKFWDRST to complete the

bus disconnection sequence.

6. After the processor is disconnected from the bus, the

system controller passes the Stop Grant special cycle along

to the peripheral controller via the PCI bus, notifying it that

the processor is in the Stop Grant state.

Figure 5 shows the signal sequence of events that take the

processor out of the Stop Grant state, reconnect the processor

to the AMD system bus, and put the processor into the Full-on

state.

Figure 5. Exiting Stop Grant State/Bus Reconnection Sequence

The following sequence of events removes the processor from

the Stop Grant state and reconnects it to the AMD system bus:

1. The peripheral controller deasserts STPCLK#, informing

the processor of a wake event.

2. When the processor receives STPCLK#, it asserts

PROCRDY, notifying the system controller to reconnect to

the bus.

3. The system controller asserts CONNECT, telling the

processor that it is connected to the AMD system bus.

4. The system controller finally deasserts CLKFWDRST, which

synchronizes the forwarded clocks between the processor

and the system controller.

STPCLK#

PROCRDY

CONNECT

CLKFWDRST

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