AMD Duron Instrukcja Użytkownika Pobierz pdf (Strona 44)

32 Signal and Power-Up Requirements Chapter 7

AMD Duron™ Processor Data Sheet 23802E—September 2000

Preliminary Information

Figure 10. Signal Relationship Requirements during Power-Up Sequence

Required Sequence. Many Southbridges (peripheral controllers)

assert RESET# and NB_RESET# (for example, PCIRST#) as

soon as possible after receiving power. The system clock

generator produces a clock soon after it has valid power (see the

specific system clock data sheets for more information).

Typically, they generate the system clocks 3ms

after receiving a

valid power level (that is, 3.3V) from the motherboard. In

addition, the motherboard must pull the open-drain system

clocks (SYSCLK/SYSCLK#) to VCC_CORE. Because the AMD

ATX Power Supply Specification requires 3.3V to be valid prior

to VCC_CORE, the motherboard must assert PWROK only after

a valid system clock is generated. To accommodate a variety of

system parameters, it is recommended that PWROK should

assert only after at least 3ms past a valid VCC_CORE (a valid

system clock).

When PWROK is asserted, the processor PLL turns on and

begins to lock. After a specified period to ensure the PLL has

locked, the reset signals can be deasserted.

3.3V Supply

VCCA (2.5V)

(for PLL)

RESET#

1.6V Supply

(Processor Core)

NB_RESET#

PWROK

System Clock

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AMD Duron Instrukcja Użytkownika Strona 44