AMD Duron Instrukcja Użytkownika Pobierz pdf (Strona 39)

Chapter 6 Electrical Data 27

23802E—September 2000 AMD Duron™ Processor Data Sheet

Preliminary Information

6.13 General AC and DC Characteristics

Table 14 shows the AC and DC characteristics of the

AMD Duron processor Southbridge, JTAG, test, and

miscellaneous pins.

Table 14. General AC and DC Characteristics*

Symbol Parameter Description Condition Min Max Units Notes

Input High Voltage

(VCC_CORE/2) +

200mV

VCC_CORE +

300mV

V1,2

Input Low Voltage –300 350 mV 1,2

Delta V

Hysteresis change in V

180 250 mV

Output High Voltage

VCC_CORE –

400

VCC_CORE +

300

Output Low Voltage –300 400 mV

LEAK_P

Tristate Leakage Pullup

= VSS

(Ground)

–1mA

LEAK_N

Tristate Leakage Pulldown

= VCC_CORE

Nominal

600

µA

Output High Current –16 mA 4

Output Low Current 16 mA 4

Sync Input Setup Time 2.0 ns 5, 6

Sync Input Hold Time 0.0 ps 5, 6

DELAY

Output Delay with respect to RSTCLK 0.0 6.1 ns 6

Notes:

* These parameters were not characterized at VCC_CORE

SLEEP

1. Characterized across DC supply voltage range.

2. Values specified at nominal VCC_CORE. Scale parameters between VCC_CORE Min and VCC_CORE Max.

3. Hysteresis values refer to the difference between initial and return switching points.

4. I

and I

are measured at V

max and V

min, respectively.

5. Synchronous inputs/outputs are specified with respect to RSTCLK and RSTCK# at the pins.

6. These are aggregate numbers.

7. Edge rates indicate the range over which inputs were characterized.

8. In asynchronous operation, the signal must persist for this time to guarantee capture.

9. This value assumes RSTCLK frequency is 10ns ==> TBIT = 2*fRST.

10. The approximate value for standard case in normal mode operation.

11. This value is dependent on RSTCLK frequency, divisors, LowPower mode, and core frequency.

12. Reassertions of the signal within this time are not guaranteed to be seen by the core.

13. This value assumes that the skew between RSTCLK and K7CLKOUT is much less than one phase.

14. This value assumes RSTCLK and K7CLKOUT are running at the same frequency, though the processor is capable of other

configurations.

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